Sundance SMT361Q Instrukcja Użytkownika

User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001 SMT361Q User Manual

Version 1.0.2 Page 10 of 24 SMT361Q User Manual EMIF Control Registers The C6416 has two external memory interfaces (EMIFs). One of these is 64 bit

Version 1.0.2 Page 11 of 24 SMT361Q User Manual FLASH An 8MByte flash memory is provided with direct access by the DSP_A. This device contains boo

Version 1.0.2 Page 12 of 24 SMT361Q User Manual All of the external interfaces provided by the FPGA are fully described in the SMT6400 help file. T

Version 1.0.2 Page 13 of 24 SMT361Q User Manual FPGA ressources ComPorts The SMT361Q provides 6 ComPorts (0, 1, 2, 3, 4 and 5) for each DSP among w

Version 1.0.2 Page 14 of 24 SMT361Q User Manual Interrupts See SMT6400 help file SDB The SMT361Q provides two SHB available to DSP_A that are 32-bi

Version 1.0.2 Page 15 of 24 SMT361Q User Manual LED The SMT361Q has 21 LEDs. The LED D14 on the top right corner of the module always displays th

Version 1.0.2 Page 16 of 24 SMT361Q User Manual Code Composer Studio This module is fully compatible with the Code Composer Studio (CCS) debug envi

Version 1.0.2 Page 17 of 24 SMT361Q User Manual The external ambient temperature must remain between 0°C and 40°C, and the relative humidity must n

Version 1.0.2 Page 18 of 24 SMT361Q User Manual Solder Side

Version 1.0.2 Page 19 of 24 SMT361Q User Manual Connector Pinouts FPGA PROG Pin Control (JP1) The FPGA PROG pin is used to clear the FPGA configura

Version 1.0.2 Page 2 of 24 SMT361Q User Manual Revision History Date Comments Engineer Version 22/04/04 First rev, based on 365 J.V. 1.0.0 01

Version 1.0.2 Page 20 of 24 SMT361Q User Manual SHB pinout Pin Signal Signal Pin 1 SHB_CLK SHB_D0 2 3 SHB_D1 SHB_D2 4 5 SHB_D3 SHB_D4 6 7 SHB_D

Version 1.0.2 Page 21 of 24 SMT361Q User Manual FPGA Memory Map See SMT6400 help file The memory mapping is as follows: DSP_A memory map: #define

Version 1.0.2 Page 22 of 24 SMT361Q User Manual #define INTCTRL6_EXT (volatile unsigned int *)0xB00F4000 #define INTCTRL7 (volatile

Version 1.0.2 Page 23 of 24 SMT361Q User Manual FPGA Pinout See board schematics. Bibliography 1. C6000 Peripherals Reference Guide (literature

Version 1.0.2 Page 24 of 24 SMT361Q User Manual Index Architecture Description...7 Bibliography...

Version 1.0.2 Page 3 of 24 SMT361Q User Manual Table of Contents Revision History ...

Version 1.0.2 Page 4 of 24 SMT361Q User Manual Operating Conditions...

Version 1.0.2 Page 5 of 24 SMT361Q User Manual Notational Conventions C60 The terms C60, C64xx and TMS320C64xx will be used interchangeably throug

Version 1.0.2 Page 6 of 24 SMT361Q User Manual Outline Description The SMT361Q is Sundance’s 3rd generation of Texas Instruments ‘C6x DSP TIM (Texa

Version 1.0.2 Page 7 of 24 SMT361Q User Manual Block Diagram 120 I/O Pins; 16-bit Data2x Comm-Ports24 I/O pinsTimer &Control2x Comm-Ports24 I

Version 1.0.2 Page 8 of 24 SMT361Q User Manual TMS320C6416 The processor will run with zero wait states from internal SRAM. The following table sh

Version 1.0.2 Page 9 of 24 SMT361Q User Manual Clock settings An on-board crystal oscillator (X2) provides the clock used for the C60, which is the