Sundance SMT407 Instrukcja Użytkownika

User Manual; Version 1.0.2, 4/8/04; © Sundance Digital Signal Processing, Inc. 2004 SMT407 User Manual

Version 1.0.0 Page 10 of 38 SMT407 User Manual 3. Place the SMT407 module on a PMC site. (See your carrier board User Manual.)Make sure that the bo

Version 1.0.0 Page 11 of 38 SMT407 User Manual QL5064 The QuickLogic PCI bridge is installed on all configurations of SMT407. This device combines

Version 1.0.0 Page 12 of 38 SMT407 User Manual Virtex FPGA design Once the FPGA has been programmed the user may then communicate with the design b

Version 1.0.0 Page 13 of 38 SMT407 User Manual TMS320C6416T This section applies only to modules built with DSPs. The processors will run with zero

Version 1.0.0 Page 14 of 38 SMT407 User Manual The C60 contains several registers that control the external memory interfaces (EMIFs). A full descr

Version 1.0.0 Page 15 of 38 SMT407 User Manual The ROM holds boot code for the C60, configuration data for the FPGA, and optional user-defined code

Version 1.0.0 Page 16 of 38 SMT407 User Manual This device requires configuring after power-up (the Virtex technology is an SRAM based logic array)

Version 1.0.0 Page 17 of 38 SMT407 User Manual FPGA The module can be fitted with an XC2VP20, XC2VP30, XC2VP40, or XC2VP50 FPGA. Only flip-chip F

Version 1.0.0 Page 18 of 38 SMT407 User Manual Figure 5: JTAG Chain on the SMT407 Xilinx describes how to connect both download cables at: Paralle

Version 1.0.0 Page 19 of 38 SMT407 User Manual SHBs SHB Connectors The SMT407 includes two 60-pin connectors to provide SHB communication to the ou

Version 1.0.0 Page 2 of 38 SMT407 User Manual Revision History Date Comments Engineer Version 2/28/05 First released version PTM 1.0.0

Version 1.0.0 Page 20 of 38 SMT407 User Manual SHB Cable Assembly The cable is custom made by Precision Interconnect and a cable assembly solution

Version 1.0.0 Page 21 of 38 SMT407 User Manual Constraint File Signal Names According to the SUNDANCE SHB specification, 5 Byte-interfaces (from 0

Version 1.0.0 Page 22 of 38 SMT407 User Manual RSLs RSL Connector The SMT407 includes two 28-pin (14-pair) RSL connectors. The connectors are ref

Version 1.0.0 Page 23 of 38 SMT407 User Manual RSL Cable Assembly Cable assemblies with QTE connectors on one side and QSE on the other are like th

Version 1.0.0 Page 24 of 38 SMT407 User Manual Miscellaneous I/O There are four LEDs connected directly to the FPGA and four additional LEDs connec

Version 1.0.0 Page 25 of 38 SMT407 User Manual LED Designator Meaning D4 Board reset D5 DSPA LED0 (GP0) D6 DSPA LED1 (GP1) D7 DSPB LED0 (GP0)

Version 1.0.0 Page 26 of 38 SMT407 User Manual PCI VIO Voltage regulator This module must have 5V and 3.3V supplied through the PMC connectors. Ei

Version 1.0.0 Page 27 of 38 SMT407 User Manual Power Consumption Measurements were made on an SMT407 at idle with the standard FPGA configuration l

Version 1.0.0 Page 28 of 38 SMT407 User Manual FPDP Figure 9: FPDP daughter card Further details TBD Software Further details Please consult the

Version 1.0.0 Page 29 of 38 SMT407 User Manual Verification Procedures The specification (design requirements) will be tested using the following:

Version 1.0.0 Page 3 of 38 SMT407 User Manual Table of Contents Revision History ...

Version 1.0.0 Page 30 of 38 SMT407 User Manual Custom The ordering code for custom configuration is as follows: SMT407–VP50-5-x-DBoard TypeVirtex I

Version 1.0.0 Page 31 of 38 SMT407 User Manual PCB Layout Details Components placement Figure 10: SMT407 Components placement-Top view Figure 11

Version 1.0.0 Page 32 of 38 SMT407 User Manual U3 & U22: DSPB SDRAM U24: Flash U8: Xilinx FPGA and DSP Core Power Supply U1 & U20: RSL Powe

Version 1.0.0 Page 33 of 38 SMT407 User Manual Headers Pinout SHB Headers Headers are per SUNDANCE SHB specification Half Word configuration. SHB P

Version 1.0.0 Page 34 of 38 SMT407 User Manual RSL Header Headers are per RSL Spec. RSL Side 1 Pinout (LVDS only) (J2) Pin # Function Function Pin

Version 1.0.0 Page 35 of 38 SMT407 User Manual JTAG/Multilinx headers Figure 12: Location of JTAG/Multilinx header JTAG Boundary scan pinout (J4)

Version 1.0.0 Page 36 of 38 SMT407 User Manual PMC Pn4 Header Figure 13: Top View IEEE 1386 Board-to-Board Plug PMC Pn4 Pinout (LVTTL only) (P14)

Version 1.0.0 Page 37 of 38 SMT407 User Manual 49 AL13 AD17 50 51 AL12 AE17 52 53 AD16 AH16 54 55 AE16 AJ16 56 57 AJ14 AK16 58 59 AK14 A

Version 1.0.0 Page 38 of 38 SMT407 User Manual Safety This module presents no hazard to the user. EMC This module is designed to operate from with

Version 1.0.0 Page 4 of 38 SMT407 User Manual Constraint File Signal Names...

Version 1.0.0 Page 5 of 38 SMT407 User Manual SHB Pinout (LVTTL only) (J3,JA3)...

Version 1.0.0 Page 6 of 38 SMT407 User Manual Table of Figures Figure 1: SMT407 Block Diagram...

Version 1.0.0 Page 7 of 38 SMT407 User Manual Physical Properties Dimensions Single-sized PMC form factor Weight TBD g (FPGA only) TBD g (with D

Version 1.0.0 Page 8 of 38 SMT407 User Manual Introduction Related Documents [1] PCI Mezzanine Card (PMC) Spec – IEEE. http://shop.ieee.org/store/

Version 1.0.0 Page 9 of 38 SMT407 User Manual Mechanical Interface: PMC Standard This module conforms to the PMC standard (PCI Mezzanine Card, See