Sundance SMT310Q Instrukcja Użytkownika

User Manual (QCF42); Version 3.1, 31/03/03; © Sundance Multiprocessor Technology Ltd. 2003 SMT310Q User Manual

Version 2.1 Page 10 of 55 SMT310Q User Manual 3.2 V363EPC PCI Bridge Chip The PCI Bridge connects the host PCI bus to various devices on the loc

Version 2.1 Page 11 of 55 SMT310Q User Manual 3.6 Onboard resources 3.6.1 SDB The on-board SDB connector is accessible via the Host PCI inter

Version 2.1 Page 12 of 55 SMT310Q User Manual 4. Comports The SMT310Q gives access to all six comports on each of the four TIM sites3. All of th

Version 2.1 Page 13 of 55 SMT310Q User Manual 123450Site 1123450Site 2123450Site 3123450Site 4Host LinkABCABCABC- Quic k Switc h- FMS Connec torExt

Version 2.1 Page 14 of 55 SMT310Q User Manual The Quick Switches are controlled by the COM-SWITCH register (BAR1, offset 2416). The Quick Switch co

Version 2.1 Page 15 of 55 SMT310Q User Manual D15 D14 D13 D12 PCI-External T1C3—C_BUF T3C3-T4C0 T3C2-T4C5 T3C1-T4C4 D11 D10 D9 D8 T2C3-T3C0 T

Version 2.1 Page 16 of 55 SMT310Q User Manual 4.2 Buffered External Comport The buffer consists of an FCT245AT type device with 64mA pull-down a

Version 2.1 Page 17 of 55 SMT310Q User Manual 4.3.2 Control Register (BAR1, Offset 1416, WRITE-ONLY) The CONTROL register contains various contr

Version 2.1 Page 18 of 55 SMT310Q User Manual 4.3.3 Status Register (BAR1, Offset 1416, Read-Only) 31-22 21 20 19 18 17 16 15-12 11 10

Version 2.1 Page 19 of 55 SMT310Q User Manual 4.3.4 Interrupt Control Register (BAR1, Offset 1816) This write-only register controls the generat

Version 2.1 Page 2 of 55 SMT310Q User Manual Revision History Date Comments Engineer Version 31-10-01 Original Document SP 0.8 20-11-01 Globa

Version 2.1 Page 20 of 55 SMT310Q User Manual 5. Sundance Digital Bus (SDB) A growing number of Sundance’s Modules have an on-board SDB. A descr

Version 2.1 Page 21 of 55 SMT310Q User Manual 6. JTAG Controller The SMT310Q has an on board Test Bus Controller (TBC), an SN74ACT8990 from Texa

Version 2.1 Page 22 of 55 SMT310Q User Manual In this case, the XDS-510 compatible connector must be selected as the JTAG source by fitting a jumpe

Version 2.1 Page 23 of 55 SMT310Q User Manual 7. Global/Local Bus Transfers, DSP ↔ PCI. The traditional global bus interface on C6x DSP modules

Version 2.1 Page 24 of 55 SMT310Q User Manual The mailbox registers are on byte boundaries with offsets C016–CF16, from LB_IO_BASE. As all DSP glo

Version 2.1 Page 25 of 55 SMT310Q User Manual 7.3 DSP To Local Aperture 0 control and Accessing The quickest way to transfer information between

Version 2.1 Page 26 of 55 SMT310Q User Manual 7.4 DSP Signals AE*/DE* active low address/data enable signals driven by the SMT310Q. When the DS

Version 2.1 Page 27 of 55 SMT310Q User Manual In the timing diagram below all signals change relative to the rising LCLK signal. This signal is the

Version 2.1 Page 28 of 55 SMT310Q User Manual When running code composer applications to debug the DSP a reduction in the speed of the debugger may

Version 2.1 Page 29 of 55 SMT310Q User Manual 8. Interrupts 8.1 SMT310Q-To-PCI Interrupts TBC INTINTAINTDPCI BridgeINTDC40 IEIBF IEOBE IETBC

Version 2.1 Page 3 of 55 SMT310Q User Manual Table of Contents 1. Introduction ...

Version 2.1 Page 30 of 55 SMT310Q User Manual 8.2 PCI-To-SMT310Q Interrupts TIMIIOF0TIMIIOF1TIMIIOF 2CONTROLREGISTERCONTROL CPLDLINTLINTLINT can

Version 2.1 Page 31 of 55 SMT310Q User Manual Details of these registers can be found in the V363EPC Local Bus PCI Bridge User Manual: (http://www.

Version 2.1 Page 32 of 55 SMT310Q User Manual 9. Memory Maps All address information is given in bytes: 9.1 PCI Bus Memory Map 9.1.1 PCI B

Version 2.1 Page 33 of 55 SMT310Q User Manual 9.1.3 Memory Space Assignments (BAR2) Address Description Notes 0000000016–000FFFFF16Shared Me

Version 2.1 Page 34 of 55 SMT310Q User Manual 9.2 Local Bus Memory Map The table below illustrates the resources and their corresponding addres

Version 2.1 Page 35 of 55 SMT310Q User Manual 10. Stand-Alone Mode For the SMT310Q to operate in stand-alone mode Jumper J8 (Figure 17: Jumper F

Version 2.1 Page 36 of 55 SMT310Q User Manual 11. Specifications 11.1 Performance Figures The following performance figures are for the SMT310

Version 2.1 Page 37 of 55 SMT310Q User Manual 11.2 Relative JTAG speed Relative Emulator Speeds1.001.671.250.851.200.600.501.622.700.000.501.001

Version 2.1 Page 38 of 55 SMT310Q User Manual 12. Cables and Connectors 12.1 SDB No SDB cables are supplied with the SMT310Q. You can order th

Version 2.1 Page 39 of 55 SMT310Q User Manual Pin No. Signal Pin No. Signal 1 GND 2 DATA0 3 DATA1 4 DATA2 5 DATA3 6 DATA4 7 DATA5 8 DATA6

Version 2.1 Page 4 of 55 SMT310Q User Manual 8. Interrupts...

Version 2.1 Page 40 of 55 SMT310Q User Manual The following table shows connector pin-out and cable pair connections. This is important, as the cri

Version 2.1 Page 41 of 55 SMT310Q User Manual When the SMT310Q is configured as a Slave using the Buffered JTAG connector as a JTAG source, the bu

Version 2.1 Page 42 of 55 SMT310Q User Manual When the SMT310Q is configured as a Master, using the Buffered JTAG connector to connect to a JTAG sl

Version 2.1 Page 43 of 55 SMT310Q User Manual Pin Signal Direction Description 1 TMS Out JTAG Test mode select 2 /TRST Out JTAG Reset 3 TDI

Version 2.1 Page 44 of 55 SMT310Q User Manual 12.4 Reset and Config headers There are pairs of headers for /TIMRESET and /TIMCONFIG to allow sev

Version 2.1 Page 45 of 55 SMT310Q User Manual 13. Expansion Header (J2) The expansion header, at the opposite end of the board to the end plate,

Version 2.1 Page 46 of 55 SMT310Q User Manual 14. JTAG Interface circuits The buffered JTAG circuit on the SMT310Q allows connection between SM

Version 2.1 Page 47 of 55 SMT310Q User Manual The JTAG circuit for a slave target board is shown in Figure 15. Using the correct buffers and conne

Version 2.1 Page 48 of 55 SMT310Q User Manual 15. Firmware Upgrades The SMT310Q' series carrier boards are populated with two Xilinx CPLDs

Version 2.1 Page 49 of 55 SMT310Q User Manual • The adaptor to connect the Parallel Cable IV to the header J21 of the SMT310Q as shown in the tabl

Version 2.1 Page 5 of 55 SMT310Q User Manual 16. Checking for hardware resource conflicts... 52 1

Version 2.1 Page 50 of 55 SMT310Q User Manual Pin1 After the JTAG cable has been connected the user should run impact. Once the connection has bee

Version 2.1 Page 51 of 55 SMT310Q User Manual used by the Sundance wizard and other Sundance software to know the features of the carrier board. At

Version 2.1 Page 52 of 55 SMT310Q User Manual 16. Checking for hardware resource conflicts For 2000 and XP users: Check for any resource confl

Version 2.1 Page 53 of 55 SMT310Q User Manual If there are conflicts: • Try inserting the carrier board into another PCI slot. • Try removing

Version 2.1 Page 54 of 55 SMT310Q User Manual 17. Where’s that Jumper? Figure 17: Jumper Finder Diagram

Version 2.1 Page 55 of 55 SMT310Q User Manual 18. LED description On the SMT310Q carrier board: - LED1 indicates the direction of the transfer

Version 2.1 Page 6 of 55 SMT310Q User Manual 1. Introduction The SMT310Q is a full-length PCI board that can carry up to four, industry-standar

Version 2.1 Page 7 of 55 SMT310Q User Manual 2. Installing the SMT310Q 2.1 Software installation You should install the SMT6300 software pack

Version 2.1 Page 8 of 55 SMT310Q User Manual Figure 1 - Hardware wizard Figure 2 - Hardware wizard detected the Sundance hardware

Version 2.1 Page 9 of 55 SMT310Q User Manual 3. Hardware Overview JTAGTIM 1 TIM 2 TIM 3 TIM 4SRAMCOMPORT CONNECTION MATRIXConnectioncontrol