Sundance SMT374 Instrukcja Użytkownika

User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001 SMT374 User Manual

Version 2.2 Page 10 of 29 SMT374 User Manual A full description of the registers used to control the EMIF can be found in the DSP C6000 Peripherals

Version 2.2 Page 11 of 29 SMT374 User Manual FPGA The FPGA (Field Programmable Gate Array) is a Xilinx Virtex-II device. It implements the followi

Version 2.2 Page 12 of 29 SMT374 User Manual As DSP-B has no connection to the ROM, the programming must be done using DSP-A. To confirm that the R

Version 2.2 Page 13 of 29 SMT374 User Manual SHB The SMT374 has two SHB connectors. These interfaces operate with a fixed clock rate of 100MHz. Arc

Version 2.2 Page 14 of 29 SMT374 User Manual The addresses of the SDB registers are shown in the Virtex Memory Map, and are described in the SMT640

Version 2.2 Page 15 of 29 SMT374 User Manual CONFIG & NMI The TIM specification describes the operation of an open-collector type signal CONFIG

Version 2.2 Page 16 of 29 SMT374 User Manual Timer The TIM TCLK0 and TCLK1 signals can be routed to the DSP’s TOUT/TINP pins. The signal directio

Version 2.2 Page 17 of 29 SMT374 User Manual Code Composer This module is fully compatible with the Code Composer Studio debug and development envi

Version 2.2 Page 18 of 29 SMT374 User Manual Operating Conditions Safety The module presents no hazard to the user. EMC The module is designed to o

Version 2.2 Page 19 of 29 SMT374 User Manual Connector Positions

Version 2.2 Page 2 of 29 SMT374 User Manual Revision History Date Comments Engineer Version 07/01/03 First rev, based on 376 GP 1.0.0 08/01/0

Version 2.2 Page 20 of 29 SMT374 User Manual Virtex Memory Map The memory mapping is as follows: #define DSPA_CP0 (volatile unsigned int *)0

Version 2.2 Page 21 of 29 SMT374 User Manual #define DSPA_INTCTRL4 (volatile unsigned int *)0xB00E0000 #define DSPA_SDBINTCTRL4 (volati

Version 2.2 Page 22 of 29 SMT374 User Manual #define DSPB_IIOF (volatile unsigned int *)0xB00D8000 #define DSPB_INTCTRL4 (volatile unsi

Version 2.2 Page 23 of 29 SMT374 User Manual Connector Pin-outs Serial Ports & Other DSP I/O (JP2 connector) Pin number Signal Signal Pin nu

Version 2.2 Page 24 of 29 SMT374 User Manual SHB generic pin-out Note: - W is a short for Full Word (i.e. 32-bit Word) - Hw i

Version 2.2 Page 25 of 29 SMT374 User Manual SHBA pin-out Pin Signal Signal Pin 1 SDB0_CLK SDB0_D0 2 3 SDB0_D1 SDB0_D2 4 5 SDB0_D3 SDB0_D4 6 7

Version 2.2 Page 26 of 29 SMT374 User Manual SHBB pin-out Pin Signal Signal Pin 1 SDB2_CLK SDB2_D0 2 3 SDB2_D1 SDB2_D2 4 5 SDB2_D3 SDB2_D4 6 7

Version 2.2 Page 27 of 29 SMT374 User Manual This standard is implemented using SAMTEC QSTRIP 0.50mm Hi-speed connectors. To improve electrical p

Version 2.2 Page 28 of 29 SMT374 User Manual Data Sheets (Hyperlinks) 1. Sundance help file 2. TMS320C6201/C6701 Peripherals Reference Guide (l

Version 2.2 Page 29 of 29 SMT374 User Manual Index A Application Development, 17 Architecture, 13 Architecture Description, 8 B Block Diagram, 7 Bo

Version 2.2 Page 3 of 29 SMT374 User Manual Table of Contents Revision History ...

Version 2.2 Page 4 of 29 SMT374 User Manual Timer...

Version 2.2 Page 5 of 29 SMT374 User Manual Notational Conventions DSP The term DSP will be used throughout this document in place of TMS320C6211,

Version 2.2 Page 6 of 29 SMT374 User Manual Outline Description The SMT374 is a dual DSP, size 1 TIM offering the following features:  TMS320C6

Version 2.2 Page 7 of 29 SMT374 User Manual Block Diagram The following drawing shows the block diagram of the SMT374 module. The main components

Version 2.2 Page 8 of 29 SMT374 User Manual Architecture Description DSPs The two Texas Instruments DSPs can run up to 300MHz. Each of them is dote

Version 2.2 Page 9 of 29 SMT374 User Manual Boot Mode The two DSPs are called DSP-A and DSP-B. DSP-A is connected to the on-board flash ROM that co