Sundance SMT498 Instrukcja Użytkownika

SMT498 User Manual User Manual; Version 1.2, 11/01/05; © Sundance Digital Signal Processing Inc. 2004 Page 1

QL5064 The PCI bridge chip from QuickLogic is installed on a SMT498. This device combines a 66MHz/64-bit PCI Master/Target ASIC core with a one-ti

Virtex FPGA configuration Programming of the Virtex FPGA can be achieved over the PCI bus using the SelectMAP interface. This interface is 8-bits wid

Virtex II FPGA The module can be fitted with an XC2VP70 or XC2VP100 FPGA. Only flip-chip FF1152 package will fit on this board. The choice of FPGA w

SHBs SHB Connectors The SMT498 includes five 60-pin connectors to provide SHB communication to the outside world. All 60 pins of each SHB connector ar

D 2xTX, 1xRX TX/RX No E 2xTX, 1xRX TX/RX TX/RX Table 1 - SHB configuration Matrix The demo logic will configure SHBA, SHBB, SHBE as receivers, while S

RSLs RSL Connector The SMT498 includes two 28-pin (7-pair) RSL connectors. 28 pins (7 pairs) of each RSL connector (52 total) are routed to the F

The RSL connectors are the fastest FPGA connections available on SMT498. As RSL are based on RocketIO transceiver blocks, the speed is limited by the

System ACE SC The SMT498 FPGA PMC module is equipped with In System FPGA configuration solution called System ACE SC. As soon as the board is power

Power Supplies Due to the close packing of components between PMC Side 1 and the host module, power consumption is limited to 4.0W for 10.0mm stan

Daughter Module SMT498 has been designed to incorporate the option for a daughter module that can interface to the FPGA and provide external I/O fun

Revision History Changes Made Issue Initials 5/31/05 First release 1.0 PTM 6/1/05 Updates based on feedback 1.1 PTM 11/1/05 Update on System

PMC Standard Voltage keying The QuickLogic 5064 bridge is both 3.3V and 5V compliant. Both keying holes are provided. Connectors According to IE

The following information shall be provided on the PMC card:  5V current drawn, peak and average  3.3V current drawn, peak and average Note: While

Header Pinout PCI A 66MHz 64-bit PCI bridge will allow SMT498 to communicate with the host system. As the Local Bus has a maximum clock speed of 64MHz

45 VIO AD15 46 45 AD14 AD13 4647 AD12 AD11 48 47 M66EN AD10 4849 AD9 +5V 50 49 AD8 +3.3V 5051 GND C/BE0N 52 51 AD7 PMC-RSVD 5253 AD6

39 VIO AD44 40 39 I/O I/O 4041 AD43 AD42 42 41 I/O I/O 4243 AD41 GND 44 43 I/O I/O 4445 GND AD40 46 45 I/O I/O 4647 AD39 AD38 48 47

SHBxUSER0(19) 21 22 SHBxWEN1 SHBxREQ1 23 24 SHBxACK1 SHBxUSER1(23) 25 26 SHBxUSER1(24) SHBxUSER1(25) 27 28 SHBxUSER1(26) SHBxUSER1(27) 29 30 SHBxU

RSL Header Headers are per RSL Spec. RSL Side 1 Pinout (LVDS only) Table 7 – RSL Side 1 Pinout RSL Side 2 Pinout (LVDS only) Table 8 – RSL Sid

JTAG headers The JTAG header is used to access the XC2VP FPGA scan chain and configure the System ACE configuration solution. RSL Connectors

A JTAG In port and JTAG Out port are provided for chaining multiple modules together. A DIP switch is provided to activate the JTAG Out port. Power c

The following figures show a preliminary concept of the Side 1, Side 2, and side view of the module. Subject to change based on final design details.

List of Abbreviations Abbreviation Explanation ASIC Application Specific Integrated Circuit BOM Bill Of Materials CMC Common Mezzanine Card Comport

This module presents no hazard to the user. EMC This module is designed to operate from within an enclosed host system, which is build to provide EM

Configuring the FPGA The module will be provided with the default VHDL core burned in the Flash. On power up, the FPGA will be configured with the d

JTAG/Boundary Scan The JTAG header is provided to enable device programming via suitable software. (See board header table for JTAG pin details). Typi

System ACE SC To configure the FPGA from the Flash on power up, install the jumper pin near the PROM chip. Turn the switch 1 of S2 to ‘ON’ position an

Status Bit Encoding: Status bits (3..0) D14 D13 D12 D11 Status Definition 1 1 1 1 System busy. Cannot process JTAG commands 1 1 1 0 Successful

Creating System ACE programming file (.MPM) Once the .BIT file is generated using the normal procedure open Xilinx iMPACT software. Under mode select

b) Select size as 64Mbits as the flash can hold 64Mbits. c) Specify the name of the .MPM file and the location to store it. Page 36

d) Select ‘In Select MAP mode’. e) Select ‘CS0’ as there is only one Target FPGA on the board Page 37

f) Select ‘Configuration Addr 0’. Click Next. If multiple bitstreams are stored under different configuration addresses. The bitstream select switche

i) Click on Finish. j) Click on Yes to Generate file. k) Do not compress the file. Click OK. Once the file is generated, it will be stored in the l

Table of Contents Introduction...

Component heights... 20 Board Weight ...

Table of Figures Figure 1 - Block diagram of the SMT498. ... 8 Figure 2 –

Introduction Overview The SMT498 is Sundance’s latest FPGA PrPMC module. This module uses a Xilinx Virtex II Pro XC2VP100, which is configured to pro

Block Diagram The following diagram shows the block diagram of the SMT498. Figure 1 - Block diagram of the SMT498. Mechanical Standard PMC is a varia

Dimensions of the single-size CMC are 74.0mm wide by 149.0mm deep. SMT498 Support The SMT498 is supported by the SMT6041-498 software package availa