Sundance SMT399-160 Instrukcja Użytkownika

Sundance Multiprocessor Technology Limited Form : QCF42 User Manual Date : 6 July 2006 Unit / Module Description: Multi-output DDS based SLB Mezzani

DDS outputs are doubled and combined with Variable Gain Amplifiers (VGA). Analog signals are all single-ended and output on MMBX connectors (J13, J14,

4.5 On-board crystal. The AD9954 are clocked from a crystal (20MHz). The master DDS then passes the sampling clock to the slave DDS to ensure synchr

Figure 5 - Multi module synchronisation connectors. 4.9 Dual-tone Mode. The SMT399-160 can used as a dual-tone generator. Both DDS outputs can be m

4.11 LEDs. There are 8 LEDs on the board. Only 4 are user defined, i.e. accessible from the FPGA on the SLB base module. These 4 leds are labelled o

5.2 Reading and Writing Registers Control packets are sent to the SMT399-160 over Comport3 only in the standard firmware. This is a bi-directional in

0x11 DDS0 – Register B (0xB) – RAM Segment Control Word 0. Read-back (FPGA Register) DDS0 – Register B (0xB). 0x12 DDS0 – Register C (0xC) – RAM Seg

Word 1. 0x34 DDS1 – Register E (0xE) – RAM Segment Control Word 1. Read-back (FPGA Register) DDS1 – Register E (0xE). 0x35 DDS1 – Register F (0xF) –

Reset Register – 0x0 Setting Bit 0 Description 0 0 Normal Operation. 1 1 Keep VGA0 in Power Down mode (Gain settings preserved). Setting Bit 1

Note 0: Reset bits don’t get cleared automatically, so a device can remain reset while not used to reduce the global power consumption. Note 1: Upd

5.4.4 VGA1 Register – 0x3. For more details, refer to AD8370 datasheet. VGA1 Register – 0x3 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Revision History Issue Changes Made Date Initials 1 Original Document 08/01/2007 PSR 2 Power consumption added 12/01/2007 PSR 3 Modification:

0 Gain Mode Gain Default ‘0’ ‘0000000’ VGA3 Register – 0x5 Setting Gain Mode (Bit 7) Description 0 0 LG Mode: Low Gain. The Gain can be fro

Sine output (Bit 12) 0 0 Cosine Function. 1 1 Sine Function. DDS0 Register – 0x6 – Control Function Register Setting Clear Freq Accum (Bit 11

4) 0 0 The clock input circuitry is enabled. 1 1 The Clock input circuitry is disabled. DDS0 Register – 0x6 – Control Function Register Setting

Setting Internal Profile Control (Bit 13-11) Description Internal Profile control. DDS0 Register – 0x7 – Control Function Register Setting Loa

1 Not Used High speed synch enable Hardware Manual Sync enable Crystal Output Pin active Not Used Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ DDS0 Register – 0x

5.4.10 DDS0 Register – 0x9 – Amplitude Scale Factor. For more details, refer to AD9954 datasheet. DDS0 Register – 0x9 – Amplitude Scale Factor Byte

DDS0 Register – 0xB – Frequency Tuning Word 0 Setting Frequency Tuning Word 0 Description The frequency tuning word is a 32-bit register that co

1 Frequency Tuning Word 1[15:8] Default ‘00000000’ DDS0 Register – 0xE – Frequency Tuning Word 1 Setting Frequency Tuning Word 1 Description T

1 RAM Segment 0 Address Ramp Rate[15:8] Default ‘00000000’ 5.4.19 DDS0 Register – 0x12 – RAM Segment Control Word 0. For more details, refer to AD9

5.4.23 DDS0 Register – 0x16 – RAM Segment Control Word 2. For more details, refer to AD9954 datasheet. DDS0 Register – 0x16 – RAM Segment Control W

Table of Contents 1 Introduction...6 2 Related Documents

5.4.27 DDS0 Register – 0x1A – RAM Segment Control Word 3. For more details, refer to AD9954 datasheet. DDS0 Register – 0x1A – RAM Segment Control Wo

5.4.30 DDS0 Register – 0x1D – Falling Delta Frequency Word. For more details, refer to AD9954 datasheet. DDS0 Register – 0x1D – Falling Delta Freque

DDS0 Register – 0x1F – Rising Delta Frequency Word Setting Rising Delta Frequency Word Description The Rising Delta Frequency word is a 32-bit r

6 PCB Layout 6.1 Top View Figure 10 - Layout - Top Side. User Manual SMT399-160 Last Edited: 24/05/2007 17:12:00

6.2 Bottom View Figure 11 - Layout - Bottom Side.User Manual SMT399-160 Page 34 of 39 Last Edited: 24/05/2007 17:12:00

7 Connector Location The following diagram shows where connectors are located on the board: Figure 12 - Connector Location. User Manual SMT399-160

8 Support Packages An example code is provided with the SMT399-160, often part of one of Sundance’s software packages. The example code, if not ta

9 Physical Properties Dimensions maximum height 12.8 mm Weight 35 gramms Supply Voltages 3.3 and 5 Volts through SLB power connector. Supply

10 Safety This module presents no hazard to the user when in normal use. User Manual SMT399-160 Page 38 of 39 Last Edited: 24/05/2007 17:12:00

11 EMC This module is designed to operate from within an enclosed host system, which is build to provide EMC shielding. Operation within the EU EMC

5.4.17 DDS0 Register – 0x10 – RAM Segment Control Word 0. ...27 5.4.18 DDS0 Register – 0x11 – RAM Segment Control Wo

Table of Figures Figure 1 - Examples of applications...8 Fi

1 Introduction The SMT399-160 is a multi-output mezzanine single width module, which is able to generate sine waves at up to 160MHz. This mezzanine

2 Related Documents  AD9954 Datasheet - Analog Devices: http://www.analog.com/Analog_Root/productPage/productHome/0,2121,AD9954,00.html Sundance

3 Examples of application. The SMT399-160 module can be used in the following application: - Radio systems. Compatible with Sundance’s TIM Modules

4 Functional Description In this part, we will see the general block diagram and some comments on the main entities. 4.1 Block Diagram The followin