Sundance SMT942 Instrukcja Użytkownika
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- Spis treści
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- User Manual 1
- Revision History 2
- Table of Contents 3
- Table of Figures 6
- Precautions 6
- 1 Related Documents 8
- 2.2 Definitions 9
- 3 Functional Description 10
- 3.3 Interface Description 12
- 3.4 FPGA Design 12
- 3.4.1.3 Memory Map 13
- Register Descriptions 14
- CLOCK Register 6 0x16 18
- CLOCK Register 13 0x23 24
- CLOCK Register 17 0x27 26
- DAC Chab Register 1 0x31 29
- DAC Chab Register 0 0x40 38
- DAC Chab Register 1 0x41 39
- 4 Connectors 47
- 4.2 Location on the board 49
- 5 Footprint 50
- 6 Pinout 51
- 7 Support Packages 52
- 8 Physical Properties 53
- 9 Safety 54
Podsumowanie treści
Sundance Multiprocessor Technology Limited User Manual Form : QCF42 Date : 11 February 2009 User Manual SMT942 Last Edited: 23/08/2011 17:25:00 U
User Manual SMT942 Last Edited: 23/08/2011 17:25:00 3 Functional Description 3.1 Block Diagram SLB Base Module (In this case SMT351T)SMT942 (SL
User Manual SMT942 Page 11 of 55 Last Edited: 23/08/2011 17:25:00 3.2.1 D/A converters The main characteristics of the SMT942 are gathered into the
User Manual SMT942 Page 12 of 55 Last Edited: 23/08/2011 17:25:00 Input Voltage Level 1.5-3.3 Volts peak-to-peak. Format DC-coupled and Single-ended
User Manual SMT942 Page 13 of 55 Last Edited: 23/08/2011 17:25:00 3.4.1.2 Reading and Writing Registers Control packets are sent to the SMT94
User Manual SMT942 Page 14 of 55 Last Edited: 23/08/2011 17:25:00 0x3E DACab Register 0xE. Read-back (FPGA Register) DACab Register 0xE. DACcd Secti
User Manual SMT942 Page 15 of 55 Last Edited: 23/08/2011 17:25:00 Setting Bit 7 Description chcd trigger selection 0 0 Trigger from control register
User Manual SMT942 Page 16 of 55 Last Edited: 23/08/2011 17:25:00 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 Output0 (DAC chc&d clk1
User Manual SMT942 Page 17 of 55 Last Edited: 23/08/2011 17:25:00 Default ‘100000’ ‘0’ ‘0’ 0 Output Divider Ratio DAC chc&d clk1 and clk2 Coarse
User Manual SMT942 Page 18 of 55 Last Edited: 23/08/2011 17:25:00 Clock Register 5 0x15 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 Ou
User Manual SMT942 Page 19 of 55 Last Edited: 23/08/2011 17:25:00 0 ‘00’ No current output reduction 1 ‘01’ 20% output current reduction 2 ‘10’ 30%
User Manual SMT942 Page 2 of 55 Last Edited: 23/08/2011 17:25:00 Revision History Issue Changes Made Date Initials 1 Original document 13/11/2009
User Manual SMT942 Page 20 of 55 Last Edited: 23/08/2011 17:25:00 Default ‘0000’ ‘0011’ Reset Register 8 0x18 Setting Bit 8 Description HOLD_O
User Manual SMT942 Page 21 of 55 Last Edited: 23/08/2011 17:25:00 1 Reserved Reserved Default ‘000000’ ‘00’ 0 Reserved BIAS_DIV45 Reserved Default ‘
User Manual SMT942 Page 22 of 55 Last Edited: 23/08/2011 17:25:00 0 ‘0’ Normal mode of operation 1 ‘1’ FB Divider can be started with external REF_S
User Manual SMT942 Page 23 of 55 Last Edited: 23/08/2011 17:25:00 Default ‘01101000’ 0 Reserved Default ‘00000000’ CLOCK Register 10 0x20. Cloc
User Manual SMT942 Page 24 of 55 Last Edited: 23/08/2011 17:25:00 Setting Bit 9:8 Description Hold function reactivates after a number of referenc
User Manual SMT942 Page 25 of 55 Last Edited: 23/08/2011 17:25:00 2 ‘10’ 30% current reduction CLOCK Register 14 0x24. Clock Register 14 0x24
User Manual SMT942 Page 26 of 55 Last Edited: 23/08/2011 17:25:00 Default ‘0’ ‘0’ ‘0’ ‘0’ ‘1011’ Reset Register 16 0x26 Setting Bit 4 Descriptio
User Manual SMT942 Page 27 of 55 Last Edited: 23/08/2011 17:25:00 0 ‘0’ VCXO selected 1 ‘1’ External clock selected Setting Bit 10 Description RES
User Manual SMT942 Page 28 of 55 Last Edited: 23/08/2011 17:25:00 1 Setting Bit 12 Description nRESET_nHOLD 0 1 DAC Status DAC Chab Regi
User Manual SMT942 Page 29 of 55 Last Edited: 23/08/2011 17:25:00 Setting Bit 2 Description synchr_clkin 0 0 Synchronous mode off. 1 1 Synchronous
User Manual SMT942 Page 3 of 55 Last Edited: 23/08/2011 17:25:00 Table of Contents 1 Introduction ...
User Manual SMT942 Page 30 of 55 Last Edited: 23/08/2011 17:25:00 2 10 2ns delay. 3 11 3ns delay. Setting Bit 7:6 Description diffclk_dly 0 00 0ns
User Manual SMT942 Page 31 of 55 Last Edited: 23/08/2011 17:25:00 1 1 Adds 6dbs to the mixer gain output. Setting Bit 2 Description clkdiv shift 0
User Manual SMT942 Page 32 of 55 Last Edited: 23/08/2011 17:25:00 0 Phase add [15:8] Default ‘00000000 DAC Chab Register 4 0x34 Setting Bit 15:0
User Manual SMT942 Page 33 of 55 Last Edited: 23/08/2011 17:25:00 DAC Chab Register 7 0x37 Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1
User Manual SMT942 Page 34 of 55 Last Edited: 23/08/2011 17:25:00 DAC Chab Register 9 0x39 Setting Bit 7:3 Description QMC offset b[12:8] 0 0
User Manual SMT942 Page 35 of 55 Last Edited: 23/08/2011 17:25:00 DAC Chab Register B 0x3B. DAC Chab Register B 0x3B Byte Bit 7 Bit 6 Bit 5 Bi
User Manual SMT942 Page 36 of 55 Last Edited: 23/08/2011 17:25:00 Setting Bit 12 Description sleepa 0 ‘0’ DACA not in sleep mode. 1 ‘1’ DACA in slee
User Manual SMT942 Page 37 of 55 Last Edited: 23/08/2011 17:25:00 0 DACA Output current scale. DAC Chab Register E 0x3E. DAC Chab Register E
User Manual SMT942 Page 38 of 55 Last Edited: 23/08/2011 17:25:00 DAC Chab Register 0 0x40. DAC Chab Register 0 0x40 Byte Bit 7 Bit 6 Bit 5 Bi
User Manual SMT942 Page 39 of 55 Last Edited: 23/08/2011 17:25:00 Setting Bit 13 Description clk1c_in_ena 0 0 Pin used as PLL_LOCK status output.
User Manual SMT942 Page 4 of 55 Last Edited: 23/08/2011 17:25:00 CLOCK Register 12 – 0x22. ...
User Manual SMT942 Page 40 of 55 Last Edited: 23/08/2011 17:25:00 1 1 1 clock cycles 2 2 2 clock cycles 3 3 3 clock cycles Setting Bit 15 Descriptio
User Manual SMT942 Page 41 of 55 Last Edited: 23/08/2011 17:25:00 DAC Chab Register 3 0x43. DAC Chab Register 3 0x43 Byte Bit 7 Bit 6 Bit 5 Bi
User Manual SMT942 Page 42 of 55 Last Edited: 23/08/2011 17:25:00 0 0 Setting Bit 15:8 Description QMC gain a[7:0] 0 0 DAC Chab Register 6 0x
User Manual SMT942 Page 43 of 55 Last Edited: 23/08/2011 17:25:00 DAC Chab Register 8 0x48. DAC Chab Register 8 0x48 Byte Bit 7 Bit 6 Bit 5 Bi
User Manual SMT942 Page 44 of 55 Last Edited: 23/08/2011 17:25:00 DAC Chab Register A 0x4A Setting Bit 7:0 Description Ser_dac_data[7:0] 0 0 Se
User Manual SMT942 Page 45 of 55 Last Edited: 23/08/2011 17:25:00 DAC Chab Register C 0x4C. DAC Chab Register C 0x4C Byte Bit 7 Bit 6 Bit 5 Bi
User Manual SMT942 Page 46 of 55 Last Edited: 23/08/2011 17:25:00 0 Coarse_daca Coarse_dacb Default ‘1111’ ‘1111 DAC Chab Register D 0x4D Setti
User Manual SMT942 Page 47 of 55 Last Edited: 23/08/2011 17:25:00 3 ‘111’ n value=8. Setting Bit 7:3 Description - pll_m 0 ‘00000’ m value=1. 1 ‘000
User Manual SMT942 Page 48 of 55 Last Edited: 23/08/2011 17:25:00
User Manual SMT942 Page 49 of 55 Last Edited: 23/08/2011 17:25:00 4.2 Location on the board Figure 6 - Connectors
User Manual SMT942 Page 5 of 55 Last Edited: 23/08/2011 17:25:00 6 Pinout ...
User Manual SMT942 Page 50 of 55 Last Edited: 23/08/2011 17:25:00 5 Footprint 5.1 Top View 5.2 Bottom View
User Manual SMT942 Last Edited: 23/08/2011 17:25:00 6 Pinout
User Manual SMT942 Last Edited: 23/08/2011 17:25:00 7 Support Packages
User Manual SMT942 Last Edited: 23/08/2011 17:25:00 8 Physical Properties Dimensions Weight Supply Voltages Supply Current +12V +5V +3.
User Manual SMT942 Page 54 of 55 Last Edited: 23/08/2011 17:25:00 9 Safety This module presents no hazard to the user when in normal use.
User Manual SMT942 Last Edited: 23/08/2011 17:25:00 10 EMC This module is designed to operate from within an enclosed host system, which is build
User Manual SMT942 Page 6 of 55 Last Edited: 23/08/2011 17:25:00 Table of Figures SLB Base Module (In this case SMT351T)SMT942 (SLB Mezzanine Module
User Manual SMT942 Page 7 of 55 Last Edited: 23/08/2011 17:25:00 Introduction The SMT942 is a single width expansion TIM that plugs onto an SL
User Manual SMT942 Last Edited: 23/08/2011 17:25:00 1 Related Documents 1.1 Referenced Documents DAC datasheet: Texas Instrument DAC5688. Clock
User Manual SMT942 Last Edited: 23/08/2011 17:25:00 2 Acronyms, Abbreviations and Definitions 2.1 Acronyms and Abbreviations 2.2 Definitions
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